In the past, ΔΣ modulation circuits (data modulation circuits) have been utilized for audios, A/D converters, etc. and, for example, have been used for converting analog signals or PCM digital signals to 1-bit signals (trains).
FIG. 1A and FIG. 1B are views illustrating an example of a conventional data modulation circuit and indicate a data modulation circuit applying primary ΔΣ modulation to modulate data. Note that FIG. 1A is a block diagram of a conventional data modulation circuit, while FIG. 1B is a view for explaining the operation of a selector in a conventional data modulation circuit.
In FIG. 1A, reference numerals 100 and 101 indicates adders, 102 a quantizer (comparator), and 103 and 104 D-type flip-flops (DFF). Here, the input signal Vin is, for example, made a 7-bit digital signal (signal of 28 to 100 minus predetermined bands at the minimum and maximum sides).
As illustrated in FIG. 1A, the input signal is input to the adder 100 where it added with the output signal AZ−1[7:0] of the DFF 103. The output signal of the adder 100 is input to the adder (subtractor) 101 where the output signal YZ−1[8:0] of the DFF 104 input to the negative input of the adder 101 is subtracted (negative addition).
Here, the DFF's 103 and 104 output the signal (Z−1) delayed by exactly one cycle of the clock signal from the input signal. Further, the signal Y[1:0] is the output signal Vout[1:0] of the output circuit part 102, while the signal A[7:0] is the output signal of the adder 101. Note that [8:0] indicates an 8-bit signal, [7:0] indicates a 7-bit signal, and [1:0] indicates a 1-bit signal.
The adder 100, for example, adds an input signal Vin[7:0] from 28 to 100 and the output of the DFF 103, that is, the signal AZ−1[7:0] has the processing signal A delayed by 1 clock. Further, the adder 101 subtracts from the output signal of the adder 100 the signal BZ−1[8:0] having the processing signal AB output by the DFF 104 delayed by 1 clock.
Further, the output circuit part 102 discriminates and quantizes the output signal A[7:0] of the adder 101 by a predetermined threshold value. That is, as illustrated in FIG. 1B, the output circuit part 102, for example, outputs Y[1:0]=00 in the case where the input signal (output signal of the adder 101) A[7:0] is “less than 0” (A2[7:0]<0), outputs Y[1:0]=01 in the case where “0 to 63” (0≦B2[7:0]≦63), and outputs Y[1:0]=10 in the case where “64 to 128” (64≦B2[7:0]≦128).
The selector 105 receives as input the output signal Y[1:0] of the output circuit part 102 and outputs the signal B[8:0]. Further, the output signal B[8:0] of the selector 105 is made, for example, B[8:0]=0 in the case where Y[1:0]=00, is made B[8:0]=64 in the case where Y[1:0]=01, and is made B[8:0]=128 in the case where Y[1:0]=10 by the output signal Y[1:0] of the output circuit part 102. Further, the DFF 104 delays the signal B[8:0] by 1 clock and outputs the signal BZ−1[8:0].
FIG. 2A and FIG. 2B are views for explaining the operation of the data modulation circuit illustrated in FIG. 1A, where FIG. 2A illustrates the change in the time-series signals (AZ−1, A, Y[1:0], BZ−1, B) for the first to 10th clocks 1 to 10 when inputting “100” to the input Vin, while FIG. 2B illustrates the change in the time-series signals for the first to 10th clocks 1 to 10 when inputting “28” to the input Vin.
Here, if the input signal Vin is X and the quantized error of the output circuit part 102 is Q, the result becomes:A=AZ−1−YZ−1+X  (1)Y=A+Q  (2)
If entering formula (2) into formula (1):Y−Q=(Y−Q)Z−1−YZ−1+X 
Therefore, the following is obtainedY=X+(1−Z−1)Q  (3)
Note that Y[1:0]=00 indicates that the signal A is “0”, Y[1:0]=01 indicates that the signal A is “64”, and Y[1:0]=10 indicates that the signal A is “128”.
In the case of the ΔΣ demodulator, if dividing the sum of the number of the Y[1:0]=01 of a certain time×64 and the number of Y[1:0]=10×128 by the number of clocks, it is possible to demodulate the input signal.
Specifically, for example, in the case of FIG. 2A, it is learned that there are six Y[1:0]=10 and four Y[1:0]=01 in 10 clocks, so (128×6+64×4)/10=102.4 and the input signal 100 can be expressed by a 1-bit signal.
Further, for example, in the case of FIG. 2B, it is learned that there are five Y[1:0]=01 and five Y[1:0]=00 in 10 clocks, so (64×5+0×5)/10=32 and the input signal 28 can be expressed by a 1-bit signal.
Note that these values can express values approximating “100” and “28” as the number of clocks becomes greater.
In this regard, in the past, as a ΔΣ demodulator able to maintain a high conversion precision (linearity) by a low over sampling ratio and reduce the number of analog devices, there is proposed one providing a digital ΔΣ demodulator at the back end of an analog ΔΣ demodulator and feeding back a signal obtained by delaying 1-bit output of the digital ΔΣ demodulator to the front-end analog ΔΣ demodulator (see, for example, Japanese Laid-open Patent Publication No. 2001-094429).
Furthermore, in the past, there is also proposed a high speed over sample modulation circuit simplifying the quantizer so as to slash the number of bits of the processing circuit and realize multibit signal processing and high speed processing without increasing the circuit size (see, for example, Japanese Laid-open Patent Publication No. 2004-147074).
This high speed over sample modulation circuit includes an adder for adding an input signal of a plurality of bits and a first feedback signal, and a subtractor subtracting a second feedback signal from a first signal of a predetermined number of bits at the higher side in the output signal from the adder.
Further, the high speed over sample modulation circuit includes a first delay device, a quantizer and a second delay device. The first delay device delays a first signal having a second signal comprised of the remaining bits at the lower side of the output signal of the adder as its lower bits and having the output signal of the subtractor as its higher bits to output a first feedback signal.
The quantizer receives a third signal as input for quantization processing and outputting a quantization signal of a predetermined number of bits, and the second delay device delays the quantization signal to output a second feedback signal.
The quantizer is designed to select specific bits in the third signal to output the quantization signal.
The conventional data modulation circuit explained with reference to FIG. 1A, FIG. 1B, FIG. 2A, and FIG. 2B has to perform processing through the adders 100 and 101 and the output circuit part 102 from when the input signal Vin[7:0](X) is input to when the output signal Vout[1:0](Y[1:0]) is output. As systems become higher in speed and greater in number of bits, it becomes difficult for these processings to be completed within 1 clock.